102 lines
3.9 KiB
C++
102 lines
3.9 KiB
C++
/* Copyright 2019 The TensorFlow Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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==============================================================================*/
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#ifndef TENSORFLOW_LITE_MICRO_KERNELS_MICRO_OPS_H_
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#define TENSORFLOW_LITE_MICRO_KERNELS_MICRO_OPS_H_
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#include "tensorflow/lite/c/common.h"
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// Forward declaration of all micro op kernel registration methods. These
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// registrations are included with the standard `BuiltinOpResolver`.
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//
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// This header is particularly useful in cases where only a subset of ops are
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// needed. In such cases, the client can selectively add only the registrations
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// their model requires, using a custom `(Micro)MutableOpResolver`. Selective
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// registration in turn allows the linker to strip unused kernels.
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namespace tflite {
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// TFLM is incrementally moving towards a flat tflite namespace
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// (https://abseil.io/tips/130). Any new ops (or cleanup of existing ops should
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// have their Register function declarations in the tflite namespace.
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TfLiteRegistration Register_CONV_2D();
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TfLiteRegistration Register_DEPTHWISE_CONV_2D();
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TfLiteRegistration Register_QUANTIZE();
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TfLiteRegistration Register_SHAPE();
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TfLiteRegistration Register_SOFTMAX();
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TfLiteRegistration Register_SVDF();
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TfLiteRegistration Register_TRANSPOSE_CONV_2D();
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namespace ops {
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namespace micro {
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TfLiteRegistration Register_ABS();
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TfLiteRegistration Register_ADD();
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TfLiteRegistration Register_ARG_MAX();
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TfLiteRegistration Register_ARG_MIN();
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TfLiteRegistration Register_AVERAGE_POOL_2D();
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TfLiteRegistration Register_CEIL();
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// TODO(b/160234179): Change custom OPs to also return by value.
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TfLiteRegistration* Register_CIRCULAR_BUFFER();
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TfLiteRegistration Register_CONCATENATION();
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TfLiteRegistration Register_COS();
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TfLiteRegistration Register_DEQUANTIZE();
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TfLiteRegistration Register_EQUAL();
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TfLiteRegistration Register_FLOOR();
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TfLiteRegistration Register_GREATER();
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TfLiteRegistration Register_GREATER_EQUAL();
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TfLiteRegistration Register_HARD_SWISH();
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TfLiteRegistration Register_LESS();
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TfLiteRegistration Register_LESS_EQUAL();
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TfLiteRegistration Register_LOG();
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TfLiteRegistration Register_LOGICAL_AND();
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TfLiteRegistration Register_LOGICAL_NOT();
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TfLiteRegistration Register_LOGICAL_OR();
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TfLiteRegistration Register_LOGISTIC();
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TfLiteRegistration Register_MAXIMUM();
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TfLiteRegistration Register_MAX_POOL_2D();
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TfLiteRegistration Register_MEAN();
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TfLiteRegistration Register_MINIMUM();
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TfLiteRegistration Register_MUL();
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TfLiteRegistration Register_NEG();
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TfLiteRegistration Register_NOT_EQUAL();
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TfLiteRegistration Register_PACK();
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TfLiteRegistration Register_PAD();
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TfLiteRegistration Register_PADV2();
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TfLiteRegistration Register_PRELU();
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TfLiteRegistration Register_REDUCE_MAX();
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TfLiteRegistration Register_RELU();
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TfLiteRegistration Register_RELU6();
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TfLiteRegistration Register_RESHAPE();
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TfLiteRegistration Register_RESIZE_NEAREST_NEIGHBOR();
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TfLiteRegistration Register_ROUND();
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TfLiteRegistration Register_RSQRT();
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TfLiteRegistration Register_SIN();
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TfLiteRegistration Register_SPLIT();
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TfLiteRegistration Register_SPLIT_V();
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TfLiteRegistration Register_SQRT();
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TfLiteRegistration Register_SQUARE();
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TfLiteRegistration Register_STRIDED_SLICE();
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TfLiteRegistration Register_SUB();
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TfLiteRegistration Register_UNPACK();
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TfLiteRegistration Register_L2_NORMALIZATION();
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TfLiteRegistration Register_TANH();
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} // namespace micro
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} // namespace ops
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} // namespace tflite
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#endif // TENSORFLOW_LITE_MICRO_KERNELS_MICRO_OPS_H_
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