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add a new config option sycl_nodouble for SYCL build (#11234)

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* add a new config option sycl_nodouble for SYCL build

When TF is built with SYCL enabled, the SYCL device code is generated
at build time. Currently, all the data types such as float and double
are registered to generate the device code.

The SYCL device code is compiled into SPIR at build time, and then
passed to OpenCL implemenation at runtime. Since double precision is
an optional feature in the OpenCL spec, it is possible that an OpenCL
implemenation does not support double.

To make some platforms without double support work, this new config
option disables double register for SYCL device code.

This patch just changes the cwise_add operation as an example, and
other operations will be changed in future small patches one by one.

* change action_env to cxxopt in tools/bazel.rc to pass the build option

* correct naming and refine #ifdef into a common place

Rename SYCL_NO_DOUBLE to TENSORFLOW_SYCL_NO_DOUBLE.
Refine #ifdef to cwise_ops_common.h, so the enable/disable of double
operation is defined in a single place for all the cwise ops.

* add TF_CALL_SYCL_NUMBER_TYPES to unify the sycl kernel register

* also consider __ANDROID_TYPES_SLIM__

another thing need to mention is that, once all cwise ops finished,
the REGISTER* defined within __ANDROID_TYPES_SLIM__ in file
cwise_ops_common.h will be defined as empty. Anyway, this will be
in another patch.
This commit is contained in:
Guo Yejun (郭叶军) 2017-07-15 09:05:18 +08:00 committed by drpngx
parent 9358451d34
commit ac98d11840
3 changed files with 20 additions and 1 deletions
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14
tensorflow/core/framework/register_types.h
View File

@ -183,4 +183,18 @@ limitations under the License.
#define TF_CALL_QUANTIZED_TYPES(m) \
TF_CALL_qint8(m) TF_CALL_quint8(m) TF_CALL_qint32(m)
#ifdef TENSORFLOW_SYCL_NO_DOUBLE
#define TF_CALL_SYCL_double(m)
#else // TENSORFLOW_SYCL_NO_DOUBLE
#define TF_CALL_SYCL_double(m) TF_CALL_double(m)
#endif // TENSORFLOW_SYCL_NO_DOUBLE
#ifdef __ANDROID_TYPES_SLIM__
#define TF_CALL_SYCL_NUMBER_TYPES(m) TF_CALL_float(m)
#else // __ANDROID_TYPES_SLIM__
#define TF_CALL_SYCL_NUMBER_TYPES(m) \
TF_CALL_float(m) \
TF_CALL_SYCL_double(m)
#endif // __ANDROID_TYPES_SLIM__
#endif // TENSORFLOW_FRAMEWORK_REGISTER_TYPES_H_

4
tensorflow/core/kernels/cwise_op_add_1.cc
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@ -36,7 +36,9 @@ REGISTER_KERNEL_BUILDER(Name("Add")
#if TENSORFLOW_USE_SYCL
REGISTER2(BinaryOp, SYCL, "Add", functor::add, float, double);
#define REGISTER_KERNEL(type) REGISTER(BinaryOp, SYCL, "Add", functor::add, type);
TF_CALL_SYCL_NUMBER_TYPES(REGISTER_KERNEL);
REGISTER_KERNEL_BUILDER(Name("Add")
.Device(DEVICE_SYCL)
.HostMemory("x")

3
tools/bazel.rc
View File

@ -11,6 +11,9 @@ build:mkl --define=using_mkl=true
build:sycl --crosstool_top=@local_config_sycl//crosstool:toolchain
build:sycl --define=using_sycl=true
build:sycl_nodouble --crosstool_top=@local_config_sycl//crosstool:toolchain
build:sycl_nodouble --define=using_sycl=true --cxxopt -DTENSORFLOW_SYCL_NO_DOUBLE
build:sycl_asan --crosstool_top=@local_config_sycl//crosstool:toolchain
build:sycl_asan --define=using_sycl=true --copt -fno-omit-frame-pointer --copt -fsanitize-coverage=3 --copt -DGPR_NO_DIRECT_SYSCALLS --linkopt -fPIC --linkopt -fsanitize=address