From ac98d1184008e4e6c2e58a3edc503d1c2c7a0e56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guo=20Yejun=20=28=E9=83=AD=E5=8F=B6=E5=86=9B=29?= Date: Sat, 15 Jul 2017 09:05:18 +0800 Subject: [PATCH] add a new config option sycl_nodouble for SYCL build (#11234) * add a new config option sycl_nodouble for SYCL build When TF is built with SYCL enabled, the SYCL device code is generated at build time. Currently, all the data types such as float and double are registered to generate the device code. The SYCL device code is compiled into SPIR at build time, and then passed to OpenCL implemenation at runtime. Since double precision is an optional feature in the OpenCL spec, it is possible that an OpenCL implemenation does not support double. To make some platforms without double support work, this new config option disables double register for SYCL device code. This patch just changes the cwise_add operation as an example, and other operations will be changed in future small patches one by one. * change action_env to cxxopt in tools/bazel.rc to pass the build option * correct naming and refine #ifdef into a common place Rename SYCL_NO_DOUBLE to TENSORFLOW_SYCL_NO_DOUBLE. Refine #ifdef to cwise_ops_common.h, so the enable/disable of double operation is defined in a single place for all the cwise ops. * add TF_CALL_SYCL_NUMBER_TYPES to unify the sycl kernel register * also consider __ANDROID_TYPES_SLIM__ another thing need to mention is that, once all cwise ops finished, the REGISTER* defined within __ANDROID_TYPES_SLIM__ in file cwise_ops_common.h will be defined as empty. Anyway, this will be in another patch. --- tensorflow/core/framework/register_types.h | 14 ++++++++++++++ tensorflow/core/kernels/cwise_op_add_1.cc | 4 +++- tools/bazel.rc | 3 +++ 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/tensorflow/core/framework/register_types.h b/tensorflow/core/framework/register_types.h index 3f91642064b..973ad4544a2 100644 --- a/tensorflow/core/framework/register_types.h +++ b/tensorflow/core/framework/register_types.h @@ -183,4 +183,18 @@ limitations under the License. #define TF_CALL_QUANTIZED_TYPES(m) \ TF_CALL_qint8(m) TF_CALL_quint8(m) TF_CALL_qint32(m) +#ifdef TENSORFLOW_SYCL_NO_DOUBLE +#define TF_CALL_SYCL_double(m) +#else // TENSORFLOW_SYCL_NO_DOUBLE +#define TF_CALL_SYCL_double(m) TF_CALL_double(m) +#endif // TENSORFLOW_SYCL_NO_DOUBLE + +#ifdef __ANDROID_TYPES_SLIM__ +#define TF_CALL_SYCL_NUMBER_TYPES(m) TF_CALL_float(m) +#else // __ANDROID_TYPES_SLIM__ +#define TF_CALL_SYCL_NUMBER_TYPES(m) \ + TF_CALL_float(m) \ + TF_CALL_SYCL_double(m) +#endif // __ANDROID_TYPES_SLIM__ + #endif // TENSORFLOW_FRAMEWORK_REGISTER_TYPES_H_ diff --git a/tensorflow/core/kernels/cwise_op_add_1.cc b/tensorflow/core/kernels/cwise_op_add_1.cc index acf1f2ad491..c0fe81ef553 100644 --- a/tensorflow/core/kernels/cwise_op_add_1.cc +++ b/tensorflow/core/kernels/cwise_op_add_1.cc @@ -36,7 +36,9 @@ REGISTER_KERNEL_BUILDER(Name("Add") #if TENSORFLOW_USE_SYCL -REGISTER2(BinaryOp, SYCL, "Add", functor::add, float, double); +#define REGISTER_KERNEL(type) REGISTER(BinaryOp, SYCL, "Add", functor::add, type); +TF_CALL_SYCL_NUMBER_TYPES(REGISTER_KERNEL); + REGISTER_KERNEL_BUILDER(Name("Add") .Device(DEVICE_SYCL) .HostMemory("x") diff --git a/tools/bazel.rc b/tools/bazel.rc index e67a290cf40..414ddf2e475 100644 --- a/tools/bazel.rc +++ b/tools/bazel.rc @@ -11,6 +11,9 @@ build:mkl --define=using_mkl=true build:sycl --crosstool_top=@local_config_sycl//crosstool:toolchain build:sycl --define=using_sycl=true +build:sycl_nodouble --crosstool_top=@local_config_sycl//crosstool:toolchain +build:sycl_nodouble --define=using_sycl=true --cxxopt -DTENSORFLOW_SYCL_NO_DOUBLE + build:sycl_asan --crosstool_top=@local_config_sycl//crosstool:toolchain build:sycl_asan --define=using_sycl=true --copt -fno-omit-frame-pointer --copt -fsanitize-coverage=3 --copt -DGPR_NO_DIRECT_SYSCALLS --linkopt -fPIC --linkopt -fsanitize=address