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Configure cache control and clockgen in sparkfun edge timer initialization.

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PiperOrigin-RevId: 318160671
Change-Id: I70612a26d92b2f840f54fc808dddbf2279ab5c98
This commit is contained in:
Nat Jeffries 2020-06-24 16:10:59 -07:00 committed by TensorFlower Gardener
parent 4cdc8d04f3
commit 8e387522d5
1 changed files with 6 additions and 0 deletions

6
tensorflow/lite/micro/sparkfun_edge/micro_time.cc
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@ -47,6 +47,12 @@ constexpr int kClocksPerSecond = 12e6;
// Enables 96MHz burst mode on Sparkfun Edge. Enable in timer since most
// benchmarks and profilers want maximum performance for debugging.
void BurstModeEnable() {
am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
// Set the default cache configuration
am_hal_cachectrl_config(&am_hal_cachectrl_defaults);
am_hal_cachectrl_enable();
am_hal_burst_avail_e eBurstModeAvailable;
am_hal_burst_mode_e eBurstMode;