From 8e387522d5592df809d0242cea634a2a9dc21a16 Mon Sep 17 00:00:00 2001
From: Nat Jeffries <njeff@google.com>
Date: Wed, 24 Jun 2020 16:10:59 -0700
Subject: [PATCH] Configure cache control and clockgen in sparkfun edge timer
 initialization.

PiperOrigin-RevId: 318160671
Change-Id: I70612a26d92b2f840f54fc808dddbf2279ab5c98
---
 tensorflow/lite/micro/sparkfun_edge/micro_time.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/tensorflow/lite/micro/sparkfun_edge/micro_time.cc b/tensorflow/lite/micro/sparkfun_edge/micro_time.cc
index 6e321a77896..9987a3b9d41 100644
--- a/tensorflow/lite/micro/sparkfun_edge/micro_time.cc
+++ b/tensorflow/lite/micro/sparkfun_edge/micro_time.cc
@@ -47,6 +47,12 @@ constexpr int kClocksPerSecond = 12e6;
 // Enables 96MHz burst mode on Sparkfun Edge. Enable in timer since most
 // benchmarks and profilers want maximum performance for debugging.
 void BurstModeEnable() {
+  am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
+
+  // Set the default cache configuration
+  am_hal_cachectrl_config(&am_hal_cachectrl_defaults);
+  am_hal_cachectrl_enable();
+
   am_hal_burst_avail_e eBurstModeAvailable;
   am_hal_burst_mode_e eBurstMode;