From ff7e6399443615675a3f1182c4f2e1850008da04 Mon Sep 17 00:00:00 2001 From: Niranjan Hasabnis Date: Mon, 18 Jun 2018 09:25:00 -0700 Subject: [PATCH] [Intel MKL] Fixing MKL graph layout pass test (#20065) This PR fixes the MKL graph layout pass test which was failing because the order in which nodes in the graph are printed seems to have changed. --- tensorflow/core/graph/mkl_layout_pass_test.cc | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/tensorflow/core/graph/mkl_layout_pass_test.cc b/tensorflow/core/graph/mkl_layout_pass_test.cc index 7645b4a7f0a..fc474c0dc82 100644 --- a/tensorflow/core/graph/mkl_layout_pass_test.cc +++ b/tensorflow/core/graph/mkl_layout_pass_test.cc @@ -1901,6 +1901,11 @@ BENCHMARK(BM_MklLayoutRewritePass)->Arg(1000)->Arg(10000); #else // INTEL_MKL_ML +// NOTE: Unit tests in this file rely on a topological sorted graph for +// printing. But since sibling nodes of a node in the topologically sorted graph +// can be printed in different orders, tests may fail if the order in which +// sibling nodes are visited is changed. + namespace { const char kCPUDevice[] = "/job:a/replica:0/task:0/device:CPU:0"; @@ -2572,9 +2577,9 @@ TEST_F(MklLayoutPassTest, NodeRewrite_Concat_Input_Mkl) { "A(Input);B(Input);C(Input);D(Input);DMT/_0(Const);DMT/_1(Const);" "DMT/_2(Const);DMT/_3(Const);DMT/_4(Const);E(_MklConv2D);" "F(_MklConv2D);G(Const);H(_MklConcat);I(Zeta)|A->E;A->I;" - "A:control->DMT/_2:control;A:control->DMT/_3:control;" - "B->E:1;C->F;C:control->DMT/_0:control;C:control->DMT/_1:control;" - "D->F:1;DMT/_0->F:2;DMT/_1->F:3;DMT/_2->E:2;DMT/_3->E:3;" + "A:control->DMT/_0:control;A:control->DMT/_1:control;" + "B->E:1;C->F;C:control->DMT/_2:control;C:control->DMT/_3:control;" + "D->F:1;DMT/_0->E:2;DMT/_1->E:3;DMT/_2->F:2;DMT/_3->F:3;" "DMT/_4->H:3;E->H:1;E:2->H:4;F->H:2;F:2->H:5;G->H;" "G:control->DMT/_4:control;H->I:1"); } @@ -2681,9 +2686,9 @@ TEST_F(MklLayoutPassTest, NodeRewrite_ConcatV2_Input_Mkl) { "A(Input);B(Input);C(Input);D(Input);DMT/_0(Const);DMT/_1(Const);" "DMT/_2(Const);DMT/_3(Const);DMT/_4(Const);E(_MklConv2D);" "F(_MklConv2D);G(Const);H(_MklConcatV2);I(Zeta)|A->E;A->I;" - "A:control->DMT/_2:control;A:control->DMT/_3:control;B->E:1;C->F;" - "C:control->DMT/_0:control;C:control->DMT/_1:control;" - "D->F:1;DMT/_0->F:2;DMT/_1->F:3;DMT/_2->E:2;DMT/_3->E:3;" + "A:control->DMT/_0:control;A:control->DMT/_1:control;B->E:1;C->F;" + "C:control->DMT/_2:control;C:control->DMT/_3:control;" + "D->F:1;DMT/_0->E:2;DMT/_1->E:3;DMT/_2->F:2;DMT/_3->F:3;" "DMT/_4->H:5;E->H;E:2->H:3;E:control->DMT/_4:control;F->H:1;" "F:2->H:4;G->H:2;H->I:1"); } @@ -3060,8 +3065,8 @@ TEST_F(MklLayoutPassTest, LRN_Negative3) { "C:control->DMT/_1:control;C:control->DMT/_2:control;" "C:control->DMT/_3:control;C:control->DMT/_4:control;" "C:control->DMT/_5:control;C:control->DMT/_6:control;" - "D->E:1;D->F:2;DMT/_0->B:1;DMT/_1->F:3;DMT/_2->F:7;DMT/_3->F:4;" - "DMT/_4->F:6;DMT/_5->E:4;DMT/_6->E:5;E->G;F->G:1"); + "D->E:1;D->F:2;DMT/_0->B:1;DMT/_1->E:4;DMT/_2->E:5;DMT/_3->F:3;" + "DMT/_4->F:7;DMT/_5->F:4;DMT/_6->F:6;E->G;F->G:1"); } /* Test MaxPool->MaxPoolGrad replacement by workspace+rewrite nodes. */