experiments/STT-tensorflow
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

KernelGen for Pow

Browse Source 
This was rolled back once due to tsan violations in LLVM which are now fixed. This will produce correct results for everything except "0 ^ -X"

PiperOrigin-RevId: 353019774
Change-Id: I57c6f96fc64854db8a1b8236d2b54a7d59eba11b
This commit is contained in:
Tres Popp 2021-01-21 07:58:48 -08:00 committed by TensorFlower Gardener
parent 6c0c1e2c49
commit f3afd96a6a
6 changed files with 101 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
tensorflow/core/kernels/cwise_op_gpu_pow.cu.cc
View File

@ -19,8 +19,11 @@ limitations under the License.
namespace tensorflow {
namespace functor {
#if !defined(MLIR_GENERATED_GPU_KERNELS_ENABLED) || \
!defined(MLIR_GENERATED_EXPERIMENTAL_GPU_KERNELS_ENABLED)
DEFINE_BINARY3(pow, Eigen::half, float, double);
DEFINE_BINARY1(safe_pow_ignore_error, int64);
#endif
} // namespace functor
} // namespace tensorflow

3
tensorflow/core/kernels/cwise_op_pow.cc
View File

@ -21,7 +21,10 @@ REGISTER6(BinaryOp, CPU, "Pow", functor::pow, float, Eigen::half, bfloat16,
REGISTER2(BinaryOp, CPU, "Pow", functor::safe_pow, int32, int64);
#if GOOGLE_CUDA || TENSORFLOW_USE_ROCM
#if !defined(MLIR_GENERATED_GPU_KERNELS_ENABLED) || \
!defined(MLIR_GENERATED_EXPERIMENTAL_GPU_KERNELS_ENABLED)
REGISTER3(BinaryOp, GPU, "Pow", functor::pow, float, Eigen::half, double);
REGISTER(BinaryOp, GPU, "Pow", functor::safe_pow_ignore_error, int64);
#endif
#endif
} // namespace tensorflow

16
tensorflow/core/kernels/mlir_generated/BUILD
View File

@ -179,6 +179,7 @@ tf_kernel_library(
"gpu_op_logical_or.cc",
"gpu_op_mul.cc",
"gpu_op_not_equal.cc",
"gpu_op_pow.cc",
"gpu_op_right_shift.cc",
"gpu_op_sub.cc",
],
@ -206,6 +207,7 @@ tf_kernel_library(
":minimum_kernels",
":mul_kernels",
":not_equal_kernels",
":pow_kernels",
":right_shift_kernels",
":sub_kernels",
"//third_party/eigen3",
@ -254,7 +256,7 @@ tf_cuda_cc_test(
tf_cuda_cc_test(
name = "gpu_binary_ops_test",
size = "small",
size = "medium",
srcs = if_mlir_generated_gpu_kernels_enabled(["gpu_binary_ops_test.cc"]),
tags = tf_cuda_tests_tags() + [
"no_cuda_asan", # b/173033461
@ -745,3 +747,15 @@ gen_kernel_library(
"tan",
]
]
gen_kernel_library(
name = "pow",
tile_size = "256,1,1",
types = [
"f16",
"f32",
"f64",
"i64",
],
unroll_factors = "4",
)

49
tensorflow/core/kernels/mlir_generated/gpu_binary_ops_test.cc
View File

@ -778,5 +778,54 @@ GENERATE_DEFAULT_TESTS(Sub,
GENERATE_DEFAULT_TESTS(Sub,
/*test_name=*/Int64, int64, int64, baseline_sub)
/// Test `tf.Pow`.
template <typename T>
T baseline_pow(T lhs, T rhs) {
return std::pow(lhs, rhs);
}
template <typename T, std::enable_if_t<
llvm::is_one_of<T, Eigen::half, float, double>::value,
bool> = true>
absl::InlinedVector<T, 10> PowInput() {
return test::InputAsVector<T, double>({0.0, 0.1, 0.2, 0.3, 1.0, 2.0, 3.0});
}
template <typename T,
std::enable_if_t<llvm::is_one_of<T, int8, int16, int32, int64>::value,
bool> = true>
absl::InlinedVector<T, 10> PowInput() {
return test::InputAsVector<T, double>({-2, -1, -1, 1, 1, 3});
}
template <>
Eigen::half baseline_pow(Eigen::half lhs, Eigen::half rhs) {
return static_cast<Eigen::half>(
std::pow(static_cast<float>(lhs), static_cast<float>(rhs)));
}
GENERATE_DEFAULT_TESTS_WITH_SPECIFIC_INPUT_VALUES(Pow,
/*test_name=*/Half,
Eigen::half, Eigen::half,
PowInput<Eigen::half>(),
PowInput<Eigen::half>(),
baseline_pow)
GENERATE_DEFAULT_TESTS_WITH_SPECIFIC_INPUT_VALUES(Pow,
/*test_name=*/Float, float,
float, PowInput<float>(),
PowInput<float>(),
baseline_pow)
GENERATE_DEFAULT_TESTS_WITH_SPECIFIC_INPUT_VALUES(Pow,
/*test_name=*/Double, double,
double, PowInput<double>(),
PowInput<double>(),
baseline_pow)
GENERATE_DEFAULT_TESTS_WITH_SPECIFIC_INPUT_VALUES(Pow,
/*test_name=*/Int64, int64,
int64, PowInput<int64>(),
PowInput<int64>(),
baseline_pow)
} // namespace
} // end namespace tensorflow

25
tensorflow/core/kernels/mlir_generated/gpu_op_pow.cc Normal file
View File

@ -0,0 +1,25 @@
/* Copyright 2021 The TensorFlow Authors. All Rights Reserved.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
==============================================================================*/
#include "third_party/eigen3/unsupported/Eigen/CXX11/Tensor"
#include "tensorflow/core/kernels/mlir_generated/gpu_ops_base.h"
namespace tensorflow {
GENERATE_AND_REGISTER_BINARY_KERNEL(Pow, f16, DT_HALF, Eigen::half);
GENERATE_AND_REGISTER_BINARY_KERNEL(Pow, f32, DT_FLOAT, float);
GENERATE_AND_REGISTER_BINARY_KERNEL(Pow, f64, DT_DOUBLE, double);
GENERATE_AND_REGISTER_BINARY_KERNEL(Pow, i64, DT_INT64, int64);
} // namespace tensorflow

6
tensorflow/core/kernels/mlir_generated/op_definitions/pow.mlir.tmpl Normal file
View File

@ -0,0 +1,6 @@
func @Pow_elem_type(%arg0: tensor<*xelem_type>, %arg1: tensor<*xelem_type>)
-> tensor<*xelem_type> attributes {tf_entry, llvm.emit_c_interface} {
%0 = "tf.Pow"(%arg0, %arg1) {T = elem_type, device = ""}
: (tensor<*xelem_type>, tensor<*xelem_type>) -> tensor<*xelem_type>
return %0 : tensor<*xelem_type>
}