parent
24f4b15253
commit
988882bb84
@ -2946,20 +2946,6 @@ port::Status CudnnSupport::DoConvolve(
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"This configuration potentially produces incorrect results.");
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}
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}
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// According to the cuDNN documentation algorithm 1 only supports NHWC
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// convolutions when using INT8. It doesn't seem to check that before
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// accessing memory though, leading to unaligned accesses.
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// TODO(b/138726848): File nvidia bug and restrict this to broken versions.
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if (algorithm_desc.algo_id() ==
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CUDNN_CONVOLUTION_FWD_ALGO_IMPLICIT_PRECOMP_GEMM &&
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filter_descriptor.layout() == dnn::FilterLayout::kOutputYXInput &&
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ToCudnnDataType(element_type) != CUDNN_DATA_INT8 &&
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ToCudnnDataType(element_type) != CUDNN_DATA_INT8x4 &&
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ToCudnnDataType(element_type) != CUDNN_DATA_UINT8x4) {
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return port::Status(
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port::error::FAILED_PRECONDITION,
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"Data type not supported by algorithm configuration.");
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}
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return port::Status::OK();
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};
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