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Cleanup of TODO’s in ARC specific files

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This commit is contained in:
Dmitry Zakharov 2020-05-15 12:46:49 +03:00
parent 543c06ce41
commit 6ccf21ef6d
9 changed files with 3 additions and 15 deletions
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1
tensorflow/lite/micro/arc_emsdp/debug_log.cc
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@ -55,7 +55,6 @@ typedef volatile struct dw_uart_reg {
// to organize blocking loop for printing symbols. No input and no IRQ handling.
// See embarc_osp repository for full EMSDP uart driver.
// (https://github.com/foss-for-synopsys-dwc-arc-processors/embarc_osp)
// TODO: Consider U-Boot API to do it in a less "hacky" way.
void DbgUartSendStr(const char* s) {
DW_UART_REG* uart_reg_ptr = (DW_UART_REG*)(EMSDP_DBG_UART_BASE);
const char* src = s;

3
tensorflow/lite/micro/examples/person_detection_experimental/arc_emsdp/emsdp.lcf
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@ -1,7 +1,6 @@
# Difference with common EMSDP LCF file (to reduce data access time):
# - move data from external PSRAM to on-chip memory
# - move text from SRAM to ICCM
# - TODO: Move tensor arena to DCCM to reduce data flow between fast and extrnal memory
#
# CCMWRAP memory regions indicate unusable portions of the address space
# due to CCM memory wrapping into upper addresses beyond its size
@ -46,8 +45,6 @@ SECTIONS {
} > SRAM
GROUP BLOCK(4): {
# TODO: Move tensor arena to DCCM when it will be possible
# .tensor_arena? : {}
.Zdata? : {}
.heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:8K): {}
.stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:8K): {}

1
tensorflow/lite/micro/kernels/arc_mli/conv.cc
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@ -52,7 +52,6 @@ struct OpData {
int output_shift;
// Per channel output multiplier and shift.
// TODO(b/141139247): Allocate these dynamically when possible.
int32_t per_channel_output_multiplier[kMaxChannels];
int32_t per_channel_output_shift[kMaxChannels];

1
tensorflow/lite/micro/kernels/arc_mli/conv_slicing_test.cc
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@ -256,7 +256,6 @@ void TestConvQuantizedPerChannel(
CreateQuantizedTensor(output_data, output_dims, output_scale,
output_zero_point, "output_tensor");
// TODO(njeff): Affine Quantization Params should be set on tensor creation.
float input_scales[] = {1, input_scale};
int input_zero_points[] = {1, input_zero_point};
TfLiteAffineQuantization input_quant = {FloatArrayFromFloats(input_scales),

4
tensorflow/lite/micro/kernels/arc_mli/depthwise_conv.cc
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@ -54,7 +54,6 @@ struct OpData {
int output_shift;
// Per channel output multiplier and shift.
// TODO(b/141139247): Allocate these dynamically when possible.
int32_t per_channel_output_multiplier[kMaxChannels];
int32_t per_channel_output_shift[kMaxChannels];
@ -74,9 +73,8 @@ bool IsMliApplicable(TfLiteContext* context, const TfLiteTensor* input,
// MLI optimized version only supports int8 dataype, dilation factor of 1 and
// per-axis quantization of weights (no broadcasting/per-tensor)
// TODO: ((in_ch == filters_num) || (in_ch == 1)) is a forbidding of
// (in_ch == filters_num) || (in_ch == 1)) is a forbidding of
// channel multiplier logic for multichannel input.
// To be removed after it will be supported in MLI
bool ret_val = (filter->type == kTfLiteInt8) &&
(input->type == kTfLiteInt8) &&
(bias->type == kTfLiteInt32) &&

1
tensorflow/lite/micro/kernels/arc_mli/depthwise_conv_slicing_test.cc
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@ -152,7 +152,6 @@ void TestDepthwiseConvQuantizedPerChannel(
CreateQuantizedTensor(output_data, output_dims, output_scale,
input_zero_point, "output_tensor");
// TODO(njeff): Affine Quantization Params should be set on tensor creation.
float input_scales[] = {1, input_scale};
int input_zero_points[] = {1, input_zero_point};
TfLiteAffineQuantization input_quant = {FloatArrayFromFloats(input_scales),

1
tensorflow/lite/micro/kernels/arc_mli/fully_connected.cc
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@ -236,7 +236,6 @@ TfLiteStatus EvalQuantizedInt8(TfLiteContext* context, TfLiteNode* node,
op_params.weights_offset = -filter->params.zero_point;
op_params.output_offset = output->params.zero_point;
op_params.output_multiplier = data->output_multiplier;
// TODO(b/138810107): Figure out whether output shift should be inverted
op_params.output_shift = -data->output_shift;
op_params.quantized_activation_min = data->output_activation_min;
op_params.quantized_activation_max = data->output_activation_max;

1
tensorflow/lite/micro/kernels/arc_mli/pooling.cc
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@ -46,7 +46,6 @@ enum MliPoolingType { AveragePooling = 0, MaxPooling = 1 };
bool IsMliApplicable(TfLiteContext* context, const TfLiteTensor* input,
const TfLitePoolParams* params) {
// MLI optimized version only supports int8 dataype and no fused Relu
// TODO: subject to add mli_saturate kernel
return (input->type == kTfLiteInt8 && params->activation == kTfLiteActNone);
}

5
tensorflow/lite/micro/kernels/arc_mli/scratch_buf_mgr.cc
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@ -54,7 +54,6 @@ static void get_arc_two_buffer_sizes(int request_size_1, int request_size_2, int
} else {
// In case only one buffer is available,
// use only the max buffer, and split it.
// TODO compute optimal split ratio based on request ratio.
*grant_size_1 = maxavailable / 2;
*grant_size_2 = maxavailable / 2;
}
@ -228,7 +227,7 @@ TfLiteStatus arc_scratch_buffer_calc_slice_size_io(
const int padding_bot,
int *in_slice_height,
int *out_slice_height) {
const int height_dimension = 1; // todo: compute from rank
const int height_dimension = 1;
const int in_height = in->shape[height_dimension];
const int out_height = out->shape[height_dimension];
const int line_size_in = mli_hlp_count_elem_num(in, height_dimension + 1) * mli_hlp_tensor_element_size(in);
@ -250,7 +249,7 @@ TfLiteStatus arc_scratch_buffer_calc_slice_size_io(
// in this case only two slices are needed, so both could benefit from padding. take the MIN to get the worst case.
max_out_lines_for_input = (max_lines_in + std::min(padding_top, padding_bot) - kernel_height + 1) / stride_height;
} else {
max_out_lines_for_input = (max_lines_in - kernel_height + 1) / stride_height; // TODO add padding exceptions and test by makin fit=false;
max_out_lines_for_input = (max_lines_in - kernel_height + 1) / stride_height;
}
// Ten compute how many ouput lines fit into the output tensor.
max_lines_out = std::min(out_height, static_cast<int>(out->capacity) / line_size_out);